Cache in ARM Cortex M7: MPU Introduction

In this fourth part of cache in ARM Cortex M7, we shall discuss what is MPU and it important.

In this guide, we shall cover the following:

• What is MPU.
• Reasons to use MPU.

1. What is MPU:

•Memory Protection Unit is a piece of hardware in modern MCUs and available in ARM Cortex M7 and some ARM Cortex M4.

•Prevents a process from accessing unallocated region which could cause system crashes etc.

•Allows privileged access to defined regions which mean the process has full access to the instruction and data.

•Can be controlled with attributes.

•Monitors every transaction (including instruction fetch).

•Violation triggers fault exception.

2. Reason to use MPU:

There are several reasons to use MPU and here are the main reasons:

• Speculative Access:

Speculative access in the ARM Cortex-M7 refers to the processor’s ability to prefetch instructions and data before they are actually needed during execution. This technique is used to improve performance by reducing the time the processor spends waiting for memory accesses. The Cortex-M7 achieves this through mechanisms like branch prediction and instruction prefetching, which allow it to anticipate the next set of instructions and data that will be required based on the current execution path.

While speculative access can significantly enhance performance by ensuring that the necessary data is already in the cache when needed, it can also lead to challenges such as cache coherency issues and unintended side effects from accessing memory locations speculatively. To mitigate these challenges, careful programming and proper configuration of the Memory Protection Unit (MPU) and cache settings are essential.

In the ARM Cortex-M7, speculative access mechanisms, including read speculation, instruction speculation, and cache linefills, are integral for enhancing performance by preemptively fetching instructions and data. Here’s an in-depth look at each:

1. Speculative Read

Speculative read involves the processor predicting and fetching data from memory that it expects will be used soon. This process helps to minimize the wait times associated with memory access by preloading data into the cache before it is explicitly requested by the running program.

2. Instruction Speculation

Instruction speculation in the Cortex-M7 includes both instruction prefetching and branch prediction.

• Instruction Prefetching:
• The processor fetches instructions from memory ahead of the current execution point.
• This prefetching is done based on the anticipated flow of execution, so that the instructions are already in the pipeline when needed, reducing fetch latency.
• Branch Prediction:
• When the processor encounters a branch (conditional or unconditional), it predicts the branch’s outcome (whether it will be taken or not taken).
• Based on this prediction, it speculatively fetches and begins executing instructions from the predicted path.
• If the prediction is correct, execution proceeds without delay. If incorrect, the speculatively executed instructions are discarded, and the correct path is fetched and executed.

3. Cache Linefills

Cache linefills relate to how the processor handles data caching and memory access.

• Data Prefetching:
• The processor anticipates future data accesses based on patterns observed in the running program.
• It speculatively loads this data into the cache to ensure it is readily available, reducing the chances of cache misses and improving access times.
• Cache Linefills:
• When a cache miss occurs (i.e., the required data is not present in the cache), the processor fetches an entire line of data from memory into the cache.
• A cache line typically consists of multiple words of data. By fetching an entire line, the processor ensures that not only the requested data but also surrounding data is loaded, which might be needed soon.
• Speculative cache linefills occur when the processor predicts that certain data will be needed and preloads entire cache lines accordingly, further reducing future cache miss penalties.

Benefits of Speculative Access

• Performance Improvement:
• By prefetching instructions and data, the processor reduces the number of stalls due to memory access latency.
• This leads to more efficient pipeline utilization and faster overall execution.
• Reduced Latency:
• Speculative access minimizes the wait time for both instructions and data, ensuring smoother and quicker transitions between different stages of execution.

Challenges of Speculative Access

• Cache Coherency:
• Speculative access can lead to complexities in maintaining cache coherency, particularly in systems with multiple cores or shared resources.
• Memory Protection:
• Speculative reads and instruction fetches must respect memory protection rules to prevent security breaches and unintended access to protected memory regions.
• The Memory Protection Unit (MPU) helps enforce these rules, ensuring speculative accesses do not violate system integrity.

In summary, speculative access in the ARM Cortex-M7, encompassing speculative reads, instruction speculation, and cache linefills, is designed to enhance performance by reducing memory access delays. These techniques allow the processor to anticipate and prepare for future instructions and data needs, thereby optimizing execution efficiency.

• DMA Issues:

This part has been discussed already and how to fix the related issue.

• Task Management:

MPU can be used to handle the task in RTOS to improve the performance and robustness of the embedded systems by restricting it within defined regions and prevent access to accessing system resources.

Stay tuned.