{"id":930,"date":"2022-05-06T16:57:38","date_gmt":"2022-05-06T16:57:38","guid":{"rendered":"https:\/\/blog.embeddedexpert.io\/?p=930"},"modified":"2022-05-06T16:59:42","modified_gmt":"2022-05-06T16:59:42","slug":"working-with-stm32-and-uart-part-6-idle-line-interrupt-with-dma","status":"publish","type":"post","link":"https:\/\/blog.embeddedexpert.io\/?p=930","title":{"rendered":"Working with STM32 and UART part 6: IDLE Line interrupt with DMA"},"content":{"rendered":"\n

In pervious guides(here<\/a>), we took look how to receive 5 characters from DMA and echo back the sent characters. However, the limitation is to need the number of received character in advanced which will limit the capability of the firmware utilitized the driver. In this guide, we shall see how configure the UART to detect idle line and generate interrupt to indicate the the last character is received.<\/p>\n\n\n\n

\"\"<\/figure><\/div>\n\n\n\n

In this guide, we shall cover the following:<\/p>\n\n\n\n

<\/p>\n\n\n\n

  • What is IDLE line detection.<\/li>
  • IDLE line configuration.<\/li>
  • DMA configuration.<\/li>
  • Code.<\/li>
  • Demo.<\/li><\/ul>\n\n\n\n

    <\/p>\n\n\n\n

    <\/p>\n\n\n\n

    1. What is IDLE line detection:<\/h2>\n\n\n\n

    IDLE line event is triggered if UART RX line is inactive for one frame. The frame time depends on the baudrate. Higher baudrate, lower frame.<\/p>\n\n\n\n

    \"\"<\/figure>\n\n\n\n

    <\/p>\n\n\n\n

    <\/p>\n\n\n\n

    2. IDLE Line configuration:<\/h2>\n\n\n\n

    We start of by enabling clock access to Port A and USART2 and configure PA2 and PA3 to work in USART mode:<\/p>\n\n\n\n

    *Enable clock access to GPIOA and USART2*\/\n\tRCC->APB1ENR|=RCC_APB1ENR_USART2EN;\n\tRCC->AHB1ENR|=RCC_AHB1ENR_GPIOAEN;\n\t\/*Configure the GPIO for UART Mode*\/\n\tGPIOA->MODER|=GPIO_MODER_MODE2_1;\/\/set bit5\n\tGPIOA->MODER&=~GPIO_MODER_MODE2_0;\/\/reset bit4\n\tGPIOA->MODER|=GPIO_MODER_MODE3_1;\/\/set bit7\n\tGPIOA->MODER&=~GPIO_MODER_MODE3_0;\/\/reset bit6\n\t#define AF07 0x07\n\tGPIOA->AFR[0]|=(AF07<<GPIO_AFRL_AFSEL2_Pos)|(AF07<<GPIO_AFRL_AFSEL3_Pos); \/\/ALT7 for UART2 (PA2 and PA3)<\/pre><\/div>\n\n\n\n
    <\/p>\n\n\n\n
    Then we configure UART as following:<\/p>\n\n\n\n
    Set baud rate to 9600 and enable TX\/RT for the UART:<\/p>\n\n\n\n
    \"\"<\/figure>\n\n\n\n
    \/*Configure UART*\/\n\tUSART2->BRR  = 0x0681;    \/\/9600 @16MHz\n\tUSART2->CR1|=USART_CR1_TE|USART_CR1_RE;<\/pre><\/div>\n\n\n\n
    Enable ILDE line interrupt:<\/p>\n\n\n\n
    USART2->CR1|=USART_CR1_IDLEIE;<\/pre><\/div>\n\n\n\n
    Enable DMA for RX in CR3 as following:<\/p>\n\n\n\n
    USART2->CR3|=USART_CR3_DMAR;<\/pre><\/div>\n\n\n\n
    Enable interrupt and UART as following:<\/p>\n\n\n\n
    \tNVIC_EnableIRQ(USART2_IRQn);\n\tUSART2->CR1|=USART_CR1_UE;<\/pre><\/div>\n\n\n\n
    For uart interrupt handler:<\/p>\n\n\n\n
    void USART2_IRQHandler(void)\n{\n    if (USART2->SR & USART_SR_IDLE) {\n\n    done =1;\n    (void)USART2->DR;\n\tDMA1_Stream5->CR &= ~DMA_SxCR_EN;         \/* disable DMA1 Stream 5 *\/\n\twhile (DMA1_Stream5->CR & DMA_SxCR_EN) {} \/* wait until DMA1 Stream 5 is disabled *\/\n\n    }\n\n}<\/pre><\/div>\n\n\n\n
    In order to clear the IDLE line interrupt, we need to read the SR followed by reading the DR register.<\/p>\n\n\n\n
    <\/p>\n\n\n\n
    3. DMA configuration:<\/h2>\n\n\n\n
    The DMA configuration is similar to the previous guide and the difference is we shall not use circular mode:<\/p>\n\n\n\n
    RCC->AHB1ENR |= RCC_AHB1ENR_DMA1EN;\n\tDMA1_Stream5->CR &= DMA_SxCR_EN;         \/* disable DMA1 Stream 5 *\/\n\twhile (DMA1_Stream5->CR & DMA_SxCR_EN) {} \/* wait until DMA1 Stream 5 is disabled *\/\n\n\tDMA1->HIFCR|=DMA_HIFCR_CDMEIF5|DMA_HIFCR_CFEIF5|DMA_HIFCR_CTCIF5|DMA_HIFCR_CHTIF5|DMA_HIFCR_CTCIF5;\n\n\tDMA1_Stream5->PAR =(uint32_t)&USART2->DR;\n\tDMA1_Stream5->M0AR = (uint32_t)(&char_data[0]);\n\tDMA1_Stream5->NDTR = buffer_size;\n\n\tDMA1_Stream5->CR =(1<<27);\n\tDMA1_Stream5->CR|=(1<<10)|(1<<4);\n\tDMA1_Stream5->CR|=(1<<0);<\/pre><\/div>\n\n\n\n
    DMA interrupt handler:<\/p>\n\n\n\n
    \n\nvoid DMA1_Stream5_IRQHandler(void)\n\t\t{\n\t\tif((DMA1->HISR)&(1<<11)) \/\/DMA receive complete\n\t\t\t{\n\t\t\tDMA1->HIFCR|=(1<<11);\n\t\t\t}\n\t\t}\n<\/pre><\/div>\n\n\n\n
    <\/p>\n\n\n\n
    <\/p>\n\n\n\n
    4. Code:<\/h2>\n\n\n\n
    The entire code can be found here:<\/p>\n\n\n\n
    #include "stm32f4xx.h"\n#include <stdlib.h>\n#include <string.h>\n#include <stdio.h>\n\n#define buffer_size 100\nuint8_t char_data[buffer_size];\nvolatile uint8_t done=0,done_rec;\n#define AF07 0x07\n\nvoid UART_Write_String(char *p);\nvoid flush_buffer();\nvoid reload();\n\nint main(void)\n{\n\t\/*Enable clock access to GPIOA and USART2*\/\n\tRCC->APB1ENR|=RCC_APB1ENR_USART2EN;\n\tRCC->AHB1ENR|=RCC_AHB1ENR_GPIOAEN;\n\t\/*Configure the GPIO for UART Mode*\/\n\tGPIOA->MODER|=GPIO_MODER_MODE2_1;\/\/set bit5\n\tGPIOA->MODER&=~GPIO_MODER_MODE2_0;\/\/reset bit4\n\tGPIOA->MODER|=GPIO_MODER_MODE3_1;\/\/set bit7\n\tGPIOA->MODER&=~GPIO_MODER_MODE3_0;\/\/reset bit6\n\tGPIOA->AFR[0]|=(AF07<<GPIO_AFRL_AFSEL2_Pos)|(AF07<<GPIO_AFRL_AFSEL3_Pos); \/\/ALT7 for UART2 (PA2 and PA3)\n\n\t\/*Configure UART*\/\n\tUSART2->BRR  = 0x0681;    \/\/9600 @16MHz\n\tUSART2->CR1|=USART_CR1_TE|USART_CR1_RE;\n\tUSART2->CR1|=USART_CR1_IDLEIE;\n\tUSART2->CR3|=USART_CR3_DMAR;\n\tNVIC_EnableIRQ(USART2_IRQn);\n\tUSART2->CR1|=USART_CR1_UE;\n\t\/*Configure the DMA*\/\n\tRCC->AHB1ENR |= RCC_AHB1ENR_DMA1EN;\n\tDMA1_Stream5->CR &= DMA_SxCR_EN;         \/* disable DMA1 Stream 5 *\/\n\twhile (DMA1_Stream5->CR & DMA_SxCR_EN) {} \/* wait until DMA1 Stream 5 is disabled *\/\n\t\/*Clear DMA1_Stream5 interrupts*\/\n\tDMA1->HIFCR|=DMA_HIFCR_CDMEIF5|DMA_HIFCR_CFEIF5|DMA_HIFCR_CTCIF5|DMA_HIFCR_CHTIF5|DMA_HIFCR_CTCIF5;\n\t\/*Memory and peripheral address and number of transfers*\/\n\tDMA1_Stream5->PAR =(uint32_t)&USART2->DR;\n\tDMA1_Stream5->M0AR = (uint32_t)(&char_data[0]);\n\tDMA1_Stream5->NDTR = buffer_size;\n\t\/*Confgiure the DMA*\/\n\tDMA1_Stream5->CR =(1<<27);\n\tDMA1_Stream5->CR|=(1<<10)|(1<<4);\n\tDMA1_Stream5->CR|=(1<<0);\n\tUART_Write_String("hello world\\r\\n");\n\twhile(1)\n\t\t{\n\n\t\twhile (done==0);\n\t\tdone=0;\n\t\tUART_Write_String((char*)char_data);\n\t\tflush_buffer();\n\t\treload();\n\n\n\t\t}\n\n}\n\n\nvoid USART_write(int ch){\nwhile(!(USART2->SR&0x0080)){\n}\nUSART2->DR=(ch);\n}\n\nvoid UART_Write_String(char *p)\n\t{\n\twhile(*p!='\\0')\n{\nUSART_write(*p);\np++;\n}\n}\n\nvoid flush_buffer()\n\t{\n\tmemset(char_data, 0, buffer_size);\n\t}\n\nvoid reload()\n\t{\n\n\tDMA1->HIFCR|=DMA_HIFCR_CDMEIF5|DMA_HIFCR_CFEIF5|DMA_HIFCR_CTCIF5|DMA_HIFCR_CHTIF5|DMA_HIFCR_CTCIF5;\n\tDMA1_Stream5->PAR =(uint32_t)&USART2->DR;\n\tDMA1_Stream5->M0AR = (uint32_t)(&char_data[0]);\n\tDMA1_Stream5->NDTR = buffer_size;\n\tDMA1_Stream5->CR |= DMA_SxCR_EN;\n\t}\n\n\nvoid USART2_IRQHandler(void)\n{\n    if (USART2->SR & USART_SR_IDLE) {\n\n    done =1;\n    (void)USART2->DR;\n\tDMA1_Stream5->CR &= ~DMA_SxCR_EN;         \/* disable DMA1 Stream 5 *\/\n\twhile (DMA1_Stream5->CR & DMA_SxCR_EN) {} \/* wait until DMA1 Stream 5 is disabled *\/\n\n    }\n\n}\n\n\n\nvoid DMA1_Stream5_IRQHandler(void)\n\t\t{\n\t\tif((DMA1->HISR)&(1<<11)) \/\/DMA receive complete\n\t\t\t{\n\t\t\tDMA1->HIFCR|=(1<<11);\n\t\t\t}\n\t\t}\n<\/pre><\/div>\n\n\n\n
    <\/p>\n\n\n\n
    <\/p>\n\n\n\n
    4. Demo:<\/h2>\n\n\n\n
    \n