For example<\/strong>, let\u2019s assume the following settings:<\/p>\n\n\n\nThe FCLK is 80MHz, the PSC is 0, ARR is 1000, and the sine lookup table has 128 sample points. What would be the output sine wave frequency?<\/p>\n\n\n\n
TriggerFrequency = 80MHz \/ 1001 = 79920.08<\/p>\n\n\n\n
Output Sinewave Frequency = TriggerFrequency \/ 128 = 624.37 Hz<\/strong><\/p>\n\n\n\n<\/p>\n\n\n\n
3. Configuring DMA for DAC:<\/h2>\n\n\n\n Before we configure the DMA, we need to get which DMA is responsible for DAC.<\/p>\n\n\n\n
From STM32F407 Reference manual DMA section:<\/p>\n\n\n\nFrom the table, we can see that DMA1, Stream5 and channel 7 is responsible for DAC.<\/p>\n\n\n\n
Hence we can start by creating macros for the channel number as following:<\/p>\n\n\n\n
#define ch7 0x07<\/pre><\/div>\n\n\n\nThen we enable clock access to DMA1 as following:<\/p>\n\n\n\n
RCC->AHB1ENR|=RCC_AHB1ENR_DMA1EN;<\/pre><\/div>\n\n\n\nThen we set the following:<\/p>\n\n\n\n
\nChannel to number 7.<\/li>\n\n\n\n Memory and peripheral size to 16-bit (half-word).<\/li>\n\n\n\n Memory increment.<\/li>\n\n\n\n Circular mode<\/li>\n\n\n\n Direction from memory to peripheral.<\/li>\n<\/ul>\n\n\n\n<\/p>\n\n\n\nDMA1_Stream5->CR|=DMA_SxCR_MSIZE_0|DMA_SxCR_PSIZE_0|DMA_SxCR_MINC\n|DMA_SxCR_CIRC|DMA_SxCR_DIR_0;<\/pre><\/div>\n\n\n\nThen we set the number of transfer as following (128 in this case):<\/p>\n\n\n\n
DMA1_Stream5->NDTR=128;<\/pre><\/div>\n\n\n\nThen we set the peripheral and memory location as following:<\/p>\n\n\n\n
DMA1_Stream5->PAR=(uint32_t)&(DAC->DHR12R1);\nDMA1_Stream5->M0AR=(uint32_t)function;\n<\/pre><\/div>\n\n\n\nDisable direct mode and FIFO threshold to full:<\/p>\n\n\n\n
DMA1_Stream5->FCR |= DMA_SxFCR_DMDIS;\nDMA1_Stream5->FCR |= (DMA_SxFCR_FTH_0 | DMA_SxFCR_FTH_1);\n<\/pre><\/div>\n\n\n\n4. Configure TIM6 for DAC:<\/h2>\n\n\n\n First we enable clock access to timer6 as following:<\/p>\n\n\n\n
RCC->APB1ENR|=RCC_APB1ENR_TIM6EN;<\/pre><\/div>\n\n\n\nWe set the prescaler and ARR values as following:<\/p>\n\n\n\n
TIM6->PSC=0;\nTIM6->ARR=1;<\/pre><\/div>\n\n\n\nThen set the update event is selected as a trigger output (TRGO) in CR2 as following:<\/p>\n\n\n\n
TIM6->CR2|=TIM_CR2_MMS_1;<\/pre><\/div>\n\n\n\n<\/p>\n\n\n\n
5. Configuring DAC for DMA:<\/h2>\n\n\n\n First thing enable clock access to DAC1 and GPIOA and set PA4 as analog mode:<\/p>\n\n\n\n
RCC->AHB1ENR|=RCC_AHB1ENR_GPIOAEN;\nRCC->APB1ENR|=RCC_APB1ENR_DACEN;\nGPIOA->MODER|=GPIO_MODER_MODE4_0|GPIO_MODER_MODE4_1;<\/pre><\/div>\n\n\n\nConfigure the amplitude to be maximum of 4095:<\/p>\n\n\n\n
DAC1->CR|=DAC_CR_MAMP1_3|DAC_CR_MAMP1_1|DAC_CR_MAMP1_0|DAC_CR_MAMP1_2;<\/pre><\/div>\n\n\n\nThen select timer6 as trigger source as following:<\/p>\n\n\n\n
DAC1->CR&=~(DAC_CR_TSEL1_0|DAC_CR_TSEL1_1|DAC_CR_TSEL1_2);<\/pre><\/div>\n\n\n\nEnable DMA request as following:<\/p>\n\n\n\n
DAC1->CR|=DAC_CR_DMAEN1;<\/pre><\/div>\n\n\n\nFinally enable DAC then the DMA and finally the timer as following:<\/p>\n\n\n\n
DAC1->CR|=DAC_CR_EN1;\nDMA1_Stream5->CR|=DMA_SxCR_EN;\nTIM6->CR1|=TIM_CR1_CEN;<\/pre><\/div>\n\n\n\nVariables used for sinewave lookup table<\/p>\n\n\n\n
#define SINE_RES 128\nconst uint16_t function[SINE_RES] = { 2048, 2145, 2242, 2339, 2435, 2530, 2624, 2717, 2808, 2897,\n 2984, 3069, 3151, 3230, 3307, 3381, 3451, 3518, 3581, 3640,\n 3696, 3748, 3795, 3838, 3877, 3911, 3941, 3966, 3986, 4002,\n 4013, 4019, 4020, 4016, 4008, 3995, 3977, 3954, 3926, 3894,\n 3858, 3817, 3772, 3722, 3669, 3611, 3550, 3485, 3416, 3344,\n 3269, 3191, 3110, 3027, 2941, 2853, 2763, 2671, 2578, 2483,\n 2387, 2291, 2194, 2096, 1999, 1901, 1804, 1708, 1612, 1517,\n 1424, 1332, 1242, 1154, 1068, 985, 904, 826, 751, 679,\n 610, 545, 484, 426, 373, 323, 278, 237, 201, 169,\n 141, 118, 100, 87, 79, 75, 76, 82, 93, 109,\n 129, 154, 184, 218, 257, 300, 347, 399, 455, 514,\n 577, 644, 714, 788, 865, 944, 1026, 1111, 1198, 1287,\n 1378, 1471, 1565, 1660, 1756, 1853, 1950, 2047 };<\/pre><\/div>\n\n\n\n<\/p>\n\n\n\n
6. Code:<\/h2>\n\n\n\n The code which including pushing the frequency of the MCU to 100MHz:<\/p>\n\n\n\n
#include "stm32f4xx.h" \/\/ Device header\n#define ch7 0x07\n#define SINE_RES 128\nconst uint16_t function[SINE_RES] = { 2048, 2145, 2242, 2339, 2435, 2530, 2624, 2717, 2808, 2897,\n 2984, 3069, 3151, 3230, 3307, 3381, 3451, 3518, 3581, 3640,\n 3696, 3748, 3795, 3838, 3877, 3911, 3941, 3966, 3986, 4002,\n 4013, 4019, 4020, 4016, 4008, 3995, 3977, 3954, 3926, 3894,\n 3858, 3817, 3772, 3722, 3669, 3611, 3550, 3485, 3416, 3344,\n 3269, 3191, 3110, 3027, 2941, 2853, 2763, 2671, 2578, 2483,\n 2387, 2291, 2194, 2096, 1999, 1901, 1804, 1708, 1612, 1517,\n 1424, 1332, 1242, 1154, 1068, 985, 904, 826, 751, 679,\n 610, 545, 484, 426, 373, 323, 278, 237, 201, 169,\n 141, 118, 100, 87, 79, 75, 76, 82, 93, 109,\n 129, 154, 184, 218, 257, 300, 347, 399, 455, 514,\n 577, 644, 714, 788, 865, 944, 1026, 1111, 1198, 1287,\n 1378, 1471, 1565, 1660, 1756, 1853, 1950, 2047 };\nvoid SysClockConfig(void) \/\/set the core frequency to 100MHz\n{\n#define PLL_M 4\n#define PLL_N 168\n#define PLL_P 2\n#define PLL_Q 9\n\n__IO uint32_t StartUpCounter = 0, HSEStatus = 0;\n\n\n RCC->CR |= ((uint32_t)RCC_CR_HSEON);\n\n\n do\n {\n HSEStatus = RCC->CR & RCC_CR_HSERDY;\n StartUpCounter++;\n } while((HSEStatus == 0) && (StartUpCounter != 3000));\n\n if ((RCC->CR & RCC_CR_HSERDY) != RESET)\n {\n HSEStatus = (uint32_t)0x01;\n }\n else\n {\n HSEStatus = (uint32_t)0x00;\n }\n\n if (HSEStatus == (uint32_t)0x01)\n {\n\n RCC->APB1ENR |= RCC_APB1ENR_PWREN;\n PWR->CR &= (uint32_t)~(PWR_CR_VOS);\n\n\n RCC->CFGR |= RCC_CFGR_HPRE_DIV1;\n\n\n RCC->CFGR |= RCC_CFGR_PPRE2_DIV2;\n\n\n RCC->CFGR |= RCC_CFGR_PPRE1_DIV4;\n\n\n RCC->PLLCFGR = PLL_M | (PLL_N << 6) | (((PLL_P >> 1) -1) << 16) |\n (RCC_PLLCFGR_PLLSRC_HSE) | (PLL_Q << 24);\n\n\n RCC->CR |= RCC_CR_PLLON;\n\n\n while((RCC->CR & RCC_CR_PLLRDY) == 0)\n {\n }\n\n \/* Configure Flash prefetch, Instruction cache, Data cache and wait state *\/\n FLASH->ACR = FLASH_ACR_ICEN |FLASH_ACR_DCEN |FLASH_ACR_LATENCY_3WS;\n\n \/* Select the main PLL as system clock source *\/\n RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));\n RCC->CFGR |= RCC_CFGR_SW_PLL;\n\n \/* Wait till the main PLL is used as system clock source *\/\n while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL)\n {;}\n }\n else\n { \/* If HSE fails to start-up, the application will have wrong clock\n configuration. User can add here some code to deal with this error *\/\n }\n\n}\n\n\nint main(void)\n{\nSysClockConfig();\n\/*fill the buffer*\/\n\nRCC->AHB1ENR|=RCC_AHB1ENR_GPIOAEN;\nRCC->APB1ENR|=RCC_APB1ENR_DACEN;\nRCC->APB1ENR|=RCC_APB1ENR_TIM6EN;\nRCC->AHB1ENR|=RCC_AHB1ENR_DMA1EN;\n\nDMA1_Stream5->CR&=~DMA_SxCR_EN;\nwhile(((DMA1_Stream5->CR)&DMA_SxCR_EN)==1);\nDMA1_Stream5->CR|=(ch7<<25);\nDMA1_Stream5->CR|=DMA_SxCR_MSIZE_0|DMA_SxCR_PSIZE_0|DMA_SxCR_MINC\n|DMA_SxCR_CIRC|DMA_SxCR_DIR_0;\nDMA1_Stream5->NDTR=128;\nDMA1_Stream5->PAR=(uint32_t)&(DAC->DHR12R1);\nDMA1_Stream5->M0AR=(uint32_t)function;\n\nDMA1_Stream5->FCR |= DMA_SxFCR_DMDIS;\nDMA1_Stream5->FCR |= (DMA_SxFCR_FTH_0 | DMA_SxFCR_FTH_1);\n\nTIM6->PSC=0;\nTIM6->ARR=1;\nTIM6->CR2|=TIM_CR2_MMS_1;\n\nGPIOA->MODER|=GPIO_MODER_MODE4_0|GPIO_MODER_MODE4_1;\n\nDAC1->CR|=DAC_CR_MAMP1_3|DAC_CR_MAMP1_1|DAC_CR_MAMP1_0|DAC_CR_MAMP1_2;\nDAC1->CR&=~(DAC_CR_TSEL1_0|DAC_CR_TSEL1_1|DAC_CR_TSEL1_2);\nDAC1->CR|=DAC_CR_DMAEN1;\nDAC1->CR|=DAC_CR_TEN1;\n\/\/DAC1->CR|=DAC_CR_BOFF1;\nDAC1->CR|=DAC_CR_EN1;\nDMA1_Stream5->CR|=DMA_SxCR_EN;\nTIM6->CR1|=TIM_CR1_CEN;\n\nwhile(1)\n\t{\n\t\t\/*\n\t\tDo something else here\n\t\t*\/\n\t}\n\n\n\n\n}\n<\/pre><\/div>\n\n\n\n<\/p>\n\n\n\n
7. Results:<\/h2>\n\n\n\n After compiling and uploading the code to STM32F407 and probe PA5 using oscilloscope, you should get this sinewave with frequency near 82KHz.<\/p>\n\n\n\nHappy coding \ud83d\ude42<\/p>\n\n\n\n
<\/p>\n","protected":false},"excerpt":{"rendered":"
In the previous guide, we took a look at the internal DAC of STM32F4 (here) and we where are able to generate sawtooth using DAC and software trigger. In this guide, we shall use timer and DMA to generate sinewave using DAC. In this guide, we shall cover the following: 1. Trigger Sources of DAC: […]<\/p>\n","protected":false},"author":2,"featured_media":0,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"footnotes":""},"categories":[2,11,12],"tags":[],"class_list":["post-851","post","type-post","status-publish","format-standard","hentry","category-embedded-systems","category-peripheral-drivers","category-stm32"],"_links":{"self":[{"href":"https:\/\/blog.embeddedexpert.io\/index.php?rest_route=\/wp\/v2\/posts\/851"}],"collection":[{"href":"https:\/\/blog.embeddedexpert.io\/index.php?rest_route=\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/blog.embeddedexpert.io\/index.php?rest_route=\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/blog.embeddedexpert.io\/index.php?rest_route=\/wp\/v2\/users\/2"}],"replies":[{"embeddable":true,"href":"https:\/\/blog.embeddedexpert.io\/index.php?rest_route=%2Fwp%2Fv2%2Fcomments&post=851"}],"version-history":[{"count":3,"href":"https:\/\/blog.embeddedexpert.io\/index.php?rest_route=\/wp\/v2\/posts\/851\/revisions"}],"predecessor-version":[{"id":3032,"href":"https:\/\/blog.embeddedexpert.io\/index.php?rest_route=\/wp\/v2\/posts\/851\/revisions\/3032"}],"wp:attachment":[{"href":"https:\/\/blog.embeddedexpert.io\/index.php?rest_route=%2Fwp%2Fv2%2Fmedia&parent=851"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/blog.embeddedexpert.io\/index.php?rest_route=%2Fwp%2Fv2%2Fcategories&post=851"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/blog.embeddedexpert.io\/index.php?rest_route=%2Fwp%2Fv2%2Ftags&post=851"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}
![\"\"](\"https:\/\/www.circuitcrush.com\/wp-content\/uploads\/Digital-to-analog-converter.png\")
<\/figure><\/div>\n\n\n![\"\"](\"https:\/\/blog.embeddedexpert.io\/wp-content\/uploads\/2022\/02\/Screen-Shot-2022-02-21-at-7.01.43-PM.png\")
<\/figure>\n\n\n\n![\"\"](\"https:\/\/blog.embeddedexpert.io\/wp-content\/uploads\/2022\/03\/Screen-Shot-2022-03-25-at-4.27.52-PM-1024x441.png\")
<\/figure><\/div>\n\n\n![\"STM32](\"https:\/\/deepbluembedded.com\/wp-content\/uploads\/2020\/06\/STM32-DAC-DMA-Sine-Wave-Generator-Tutorial.png?ezimgfmt=rs:347x43\/rscb6\/ngcb6\/notWebP\")
<\/figure><\/div>\n\n\n![\"STM32](\"https:\/\/deepbluembedded.com\/wp-content\/uploads\/2020\/06\/STM32-DAC-Sine-Wave-Generator-With-DMA-And-Timer-Trigger-Tutorial.png?ezimgfmt=rs:328x39\/rscb6\/ngcb6\/notWebP\")
<\/figure><\/div>\n\n\n![\"\"](\"https:\/\/blog.embeddedexpert.io\/wp-content\/uploads\/2022\/03\/Screen-Shot-2022-03-25-at-4.37.05-PM-1024x235.png\")
<\/figure>\n\n\n\n![\"\"](\"https:\/\/blog.embeddedexpert.io\/wp-content\/uploads\/2022\/03\/Screen-Shot-2022-03-25-at-4.40.25-PM-1024x386.png\")
<\/figure>\n\n\n\n![\"\"](\"https:\/\/blog.embeddedexpert.io\/wp-content\/uploads\/2022\/03\/DS1Z_QuickPrint8.png\")
<\/figure>\n\n\n\n