{"id":531,"date":"2021-10-28T04:41:59","date_gmt":"2021-10-28T04:41:59","guid":{"rendered":"https:\/\/blog.embeddedexpert.io\/?p=531"},"modified":"2021-10-28T06:16:22","modified_gmt":"2021-10-28T06:16:22","slug":"changing-core-frequency-of-stm32f767-using-registers-only","status":"publish","type":"post","link":"https:\/\/blog.embeddedexpert.io\/?p=531","title":{"rendered":"Changing core frequency of STM32F767 using registers only"},"content":{"rendered":"\n

In this guide, we shall use registers to change the core frequency from default 16MHz to 216MHz (maximum for F767ZIT).<\/p>\n\n\n\n

\"\"<\/figure><\/div>\n\n\n\n

We shall use CubeMX to determine the values required to reach the 216MHz operation.<\/p>\n\n\n\n

1. Getting required settings from CubeMX<\/h2>\n\n\n\n

We start off by opening CubeMX and select your F7 chip (F767ZITx in my case).<\/p>\n\n\n\n

After that, select system core then RCC and set the High Speed Clock as Crystal\/Ceramic Resonator<\/p>\n\n\n\n

\"\"<\/figure>\n\n\n\n

After that, open Clock Configuration tab and follow the following steps<\/p>\n\n\n\n

\"\"<\/figure>\n\n\n\n
  • 1. Set the crystal frequency to match yours (8MHz in my case)<\/li>
  • 2. Select HSE as PLL source MUX<\/li>
  • 3. Set HCLK to 216 and hit enter<\/li><\/ul>\n\n\n\n

    Now write down the PLL_N, PLL_M and PLL_P values and also AHB1, APB1 and APB2 prescalers. In my case, I have those values:<\/p>\n\n\n\n

    #define PLL_M      4\n#define PLL_N      216\n#define PLL_P      2<\/pre><\/div>\n\n\n\n
    After that head back to RCC and note the flash latency:<\/p>\n\n\n\n
    \"\"<\/figure>\n\n\n\n
    In my case, I need to flash latency to 7WS (8-CPU cycle).<\/p>\n\n\n\n
    2. Start configuring the clock<\/h2>\n\n\n\n
    We start off by opening the project and open system_stm32f7xx.c file<\/p>\n\n\n\n
    In line HSE_VALUE change the value from 25000000 to the one match match yours (8000000 in my case)<\/p>\n\n\n\n
    \"\"<\/figure>\n\n\n\n
    Now, in main file we shall declare a function to change as following:<\/p>\n\n\n\n
    void SysClockConfig(void)<\/pre><\/div>\n\n\n\n
    It takes not argument and returns nothing.<\/p>\n\n\n\n
    Inside the function we start defining the PLL_P, PLLM and PLL_N values<\/p>\n\n\n\n
    #define PLL_M      4\n#define PLL_N      216\n#define PLL_P      2<\/pre><\/div>\n\n\n\n
    Now declare some variable to help us later<\/p>\n\n\n\n
     __IO uint32_t StartUpCounter = 0, HSEStatus = 0;<\/pre><\/div>\n\n\n\n
    We start off by enabling external clock source as following:<\/p>\n\n\n\n
    RCC->CR |= ((uint32_t)RCC_CR_HSEON);<\/pre><\/div>\n\n\n\n
    Then we wait until the clock is ready, if it is not ready within 3000 counts, break the function and jump to error section:<\/p>\n\n\n\n
    do\n  {\n    HSEStatus = RCC->CR & RCC_CR_HSERDY;\n    StartUpCounter++;\n  } while((HSEStatus == 0) && (StartUpCounter != 3000));<\/pre><\/div>\n\n\n\n
    Check if the HSE is on<\/p>\n\n\n\n
    if ((RCC->CR & RCC_CR_HSERDY) != RESET)\n  {\n    HSEStatus = (uint32_t)0x01;\n  }\n  else\n  {\n    HSEStatus = (uint32_t)0x00;\n  }<\/pre><\/div>\n\n\n\n
    if activated, we continue configuring the clock<\/p>\n\n\n\n
    We start off by enabling clock access to power interface as following:<\/p>\n\n\n\n
    RCC->APB1ENR |= RCC_APB1ENR_PWREN;<\/pre><\/div>\n\n\n\n
    Then we reset VOS which will force to mode three<\/p>\n\n\n\n
    PWR->CR1 &= (uint32_t)~(PWR_CR1_VOS);<\/pre><\/div>\n\n\n\n
    Now we set the AHB1,APB1 and APB2 prescaler as following:<\/p>\n\n\n\n
    RCC->CFGR |= RCC_CFGR_HPRE_DIV1;\n      \n\n    RCC->CFGR |= RCC_CFGR_PPRE2_DIV2;\n    \n\n    RCC->CFGR |= RCC_CFGR_PPRE1_DIV4;<\/pre><\/div>\n\n\n\n
    Then we configure the PLL as following:<\/p>\n\n\n\n
    RCC->PLLCFGR = PLL_M | (PLL_N << RCC_PLLCFGR_PLLN_Pos) | (((PLL_P >> 1) -1) << RCC_PLLCFGR_PLLP_Pos) |\n                   (RCC_PLLCFGR_PLLSRC_HSE);<\/pre><\/div>\n\n\n\n
    Now, we turn on the PLL and wait until it is on<\/p>\n\n\n\n
    RCC->CR |= RCC_CR_PLLON;\n\n    \n    while((RCC->CR & RCC_CR_PLLRDY) == 0)\n    {\n    }\n   <\/pre><\/div>\n\n\n\n
    Then we configure the flash latency to be 7WS (waiting state)<\/p>\n\n\n\n
    \/* Configure Flash prefetch, Instruction cache, Data cache and wait state *\/\n    FLASH->ACR = FLASH_ACR_LATENCY_7WS;<\/pre><\/div>\n\n\n\n
    We select the PLL as clock source <\/p>\n\n\n\n
      \/* Select the main PLL as system clock source *\/\n    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));\n    RCC->CFGR |= RCC_CFGR_SW_PLL;\n\n    \/* Wait till the main PLL is used as system clock source *\/\n    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL)\n    {;}<\/pre><\/div>\n\n\n\n
    Hence, the full code as following:<\/p>\n\n\n\n
    \nvoid SysClockConfig(void) \/\/set the core frequency to 216MHz\n{\n#define PLL_M      4\n#define PLL_N      216\n#define PLL_P      2\n\t\n__IO uint32_t StartUpCounter = 0, HSEStatus = 0;\n  \n\n  RCC->CR |= ((uint32_t)RCC_CR_HSEON);\n \n\n  do\n  {\n    HSEStatus = RCC->CR & RCC_CR_HSERDY;\n    StartUpCounter++;\n  } while((HSEStatus == 0) && (StartUpCounter != 3000));\n\n  if ((RCC->CR & RCC_CR_HSERDY) != RESET)\n  {\n    HSEStatus = (uint32_t)0x01;\n  }\n  else\n  {\n    HSEStatus = (uint32_t)0x00;\n  }\n\n  if (HSEStatus == (uint32_t)0x01)\n  {\n \n    RCC->APB1ENR |= RCC_APB1ENR_PWREN;\n    PWR->CR1 &= (uint32_t)~(PWR_CR1_VOS);\n\n\n    RCC->CFGR |= RCC_CFGR_HPRE_DIV1;\n      \n\n    RCC->CFGR |= RCC_CFGR_PPRE2_DIV2;\n    \n\n    RCC->CFGR |= RCC_CFGR_PPRE1_DIV4;\n\n\t\t\n    RCC->PLLCFGR = PLL_M | (PLL_N << RCC_PLLCFGR_PLLN_Pos) | (((PLL_P >> 1) -1) << RCC_PLLCFGR_PLLP_Pos) |\n                   (RCC_PLLCFGR_PLLSRC_HSE);\n\n\n    RCC->CR |= RCC_CR_PLLON;\n\n    \n    while((RCC->CR & RCC_CR_PLLRDY) == 0)\n    {\n    }\n   \n    \/* Configure Flash prefetch, Instruction cache, Data cache and wait state *\/\n    FLASH->ACR = FLASH_ACR_LATENCY_7WS;\n\n    \/* Select the main PLL as system clock source *\/\n    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));\n    RCC->CFGR |= RCC_CFGR_SW_PLL;\n\n    \/* Wait till the main PLL is used as system clock source *\/\n    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL)\n    {;}\n  }\n  else\n  { \/* If HSE fails to start-up, the application will have wrong clock\n         configuration. User can add here some code to deal with this error *\/\n  }\n\n\tSystemCoreClockUpdate();\n\t\n\t\n}\n\n<\/pre><\/div>\n\n\n\n
    3. Validating Core Frequency:<\/h2>\n\n\n\n
    In order to validate the core frequency, we shall use SysTick timer to generate interrupt at rate of 1KHz (each 1 millisecond) and enable clock to PORTA and set PA5 as output  as following:<\/p>\n\n\n\n
    __disable_irq();\n\t\n\tSysTick->LOAD=216000-1;\n\tSysTick->VAL=0;\n\tSysTick->CTRL=7; \/\/0b00000111;\n\tRCC->AHB1ENR |=RCC_AHB1ENR_GPIOAEN;\n\tGPIOA->MODER|= GPIO_MODER_MODER5_0; \/\/PA5 as output\n\t__enable_irq();<\/pre><\/div>\n\n\n\n
    in interrupt handler, we shall toggle PA5 as following:<\/p>\n\n\n\n
    void SysTick_Handler(void){\nGPIOA->ODR^=GPIO_ODR_OD5;\n}\t\n<\/pre><\/div>\n\n\n\n
    After compile and upload the code and probe PA5 we shall get the following:<\/p>\n\n\n\n
    \"\"<\/figure>\n\n\n\n
    Since each division of the horizontal line is 500microseconds, and we are getting 2 division high and two division low, thats mean the on time 1 millisecond and 1 millisecond off which as we set it. Thats mean we successfully changed the core frequency from 16MHz to 216MHz. Now, you can get the full potential of your mcu.<\/p>\n\n\n\n
    Happy coding<\/p>\n","protected":false},"excerpt":{"rendered":"
    In this guide, we shall use registers to change the core frequency from default 16MHz to 216MHz (maximum for F767ZIT). We shall use CubeMX to determine the values required to reach the 216MHz operation. 1. Getting required settings from CubeMX We start off by opening CubeMX and select your F7 chip (F767ZITx in my case). […]<\/p>\n","protected":false},"author":2,"featured_media":0,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"footnotes":""},"categories":[2,12],"tags":[],"class_list":["post-531","post","type-post","status-publish","format-standard","hentry","category-embedded-systems","category-stm32"],"_links":{"self":[{"href":"https:\/\/blog.embeddedexpert.io\/index.php?rest_route=\/wp\/v2\/posts\/531"}],"collection":[{"href":"https:\/\/blog.embeddedexpert.io\/index.php?rest_route=\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/blog.embeddedexpert.io\/index.php?rest_route=\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/blog.embeddedexpert.io\/index.php?rest_route=\/wp\/v2\/users\/2"}],"replies":[{"embeddable":true,"href":"https:\/\/blog.embeddedexpert.io\/index.php?rest_route=%2Fwp%2Fv2%2Fcomments&post=531"}],"version-history":[{"count":2,"href":"https:\/\/blog.embeddedexpert.io\/index.php?rest_route=\/wp\/v2\/posts\/531\/revisions"}],"predecessor-version":[{"id":539,"href":"https:\/\/blog.embeddedexpert.io\/index.php?rest_route=\/wp\/v2\/posts\/531\/revisions\/539"}],"wp:attachment":[{"href":"https:\/\/blog.embeddedexpert.io\/index.php?rest_route=%2Fwp%2Fv2%2Fmedia&parent=531"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/blog.embeddedexpert.io\/index.php?rest_route=%2Fwp%2Fv2%2Fcategories&post=531"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/blog.embeddedexpert.io\/index.php?rest_route=%2Fwp%2Fv2%2Ftags&post=531"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}