![\"\"](\"https:\/\/blog.embeddedexpert.io\/wp-content\/uploads\/2021\/09\/depositphotos_107252360-stock-illustration-maximum-speed-logo-icon-300x229.jpg\"){kind=icon}
<\/figure><\/div>\n\n\n\nWe shall use both keil uVision and STM32CubeIDE to change the core frequency to 100MHz.<\/p>\n\n\n\n
1. Open CubMX <\/h2>\n\n\n\n
After you select your MCU, head to RCC and select external oscillator<\/p>\n\n\n\n Then open clock configuration and set the external oscillator to one on your board (in my case is 8MHz).<\/p>\n\n\n\n Note the following Values:<\/p>\n\n\n\n In my case they are the following:<\/p>\n\n\n\n Open either CubeIDE or Keil uVision and start new project <\/p>\n\n\n\n Open system_stm32f4xx.c file and change the external frequency from 25MHz to one on your board (8MHz in my case).<\/p>\n\n\n\n We start of by enabling external clock and waiting for the external clock to be ready<\/p>\n\n\n\n then if the external clock is enable, proceed to change the core frequency as following<\/p>\n\n\n\n We can test the core frequency using SysTick to generate delay as following<\/p>\n\n\n\n You may download the entire project from here<\/p>\n\n\n\n Keil uVison version<\/p>\n\n\n\n![\"\"](\"https:\/\/blog.embeddedexpert.io\/wp-content\/uploads\/2021\/09\/Screen-Shot-2021-09-27-at-8.19.24-AM-1024x480.png\")
<\/figure>\n\n\n\n![\"\"](\"https:\/\/blog.embeddedexpert.io\/wp-content\/uploads\/2021\/09\/Screen-Shot-2021-09-27-at-8.25.23-AM-1024x746.png\")
<\/figure>\n\n\n\n#define PLL_M 4\n#define PLL_N 200\n#define PLL_P 4<\/pre><\/div>\n\n\n\n
2. Start new project<\/h2>\n\n\n\n
3. Open system_stm32f4xx.c<\/h2>\n\n\n\n
![\"\"](\"https:\/\/blog.embeddedexpert.io\/wp-content\/uploads\/2021\/09\/Screen-Shot-2021-09-27-at-8.29.22-AM-1024x746.png\")
<\/figure>\n\n\n\n4. Start the configuration<\/h2>\n\n\n\n
__IO uint32_t StartUpCounter = 0, HSEStatus = 0;\n\n\n RCC->CR |= ((uint32_t)RCC_CR_HSEON);\n\n\n do\n {\n HSEStatus = RCC->CR & RCC_CR_HSERDY;\n StartUpCounter++;\n } while((HSEStatus == 0) && (StartUpCounter != 3000));<\/pre><\/div>\n\n\n\nif ((RCC->CR & RCC_CR_HSERDY) != RESET) \/\/HSE enabled\n {\n HSEStatus = (uint32_t)0x01;\n }\n else\n {\n HSEStatus = (uint32_t)0x00;\n }\n\n if (HSEStatus == (uint32_t)0x01)\n {\n\n RCC->APB1ENR |= RCC_APB1ENR_PWREN; \/\/enable opwer regultor\n PWR->CR &= (uint32_t)~(PWR_CR_VOS); \/\/reset VOS (mode 3 selected)\n\n\n RCC->CFGR |= RCC_CFGR_HPRE_DIV1; \/\/configure AHB1 bus prescaler to 1\n\n\n RCC->CFGR |= RCC_CFGR_PPRE2_DIV1; \/\/APB2 prescaler to 1\n\n\n RCC->CFGR |= RCC_CFGR_PPRE1_DIV2; \/\/APB2 prescaler to 2\n\n\n RCC->PLLCFGR = PLL_M | (PLL_N << 6) | (((PLL_P >> 1) -1) << 16) | \/\/set PLL_M,PLL_N,PLL_P \n (RCC_PLLCFGR_PLLSRC_HSE) | (PLL_Q << 24);\n\n\n RCC->CR |= RCC_CR_PLLON; \/\/turn on the PLL\n\n\n while((RCC->CR & RCC_CR_PLLRDY) == 0) \/\/wait untill PLL is active\n {\n }\n\n \/* Configure Flash prefetch, Instruction cache, Data cache and wait state *\/\n FLASH->ACR = FLASH_ACR_ICEN |FLASH_ACR_DCEN |FLASH_ACR_LATENCY_3WS;\n\n \/* Select the main PLL as system clock source *\/\n RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));\n RCC->CFGR |= RCC_CFGR_SW_PLL;\n\n \/* Wait till the main PLL is used as system clock source *\/\n while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL)\n {;}\n }\n else\n { \/* If HSE fails to start-up, the application will have wrong clock\n configuration. User can add here some code to deal with this error *\/\n }<\/pre><\/div>\n\n\n\n5. Testing using SysTick delay<\/h2>\n\n\n\n
void delay(int ms)\n{\n\tSysTick->LOAD=100000-1;\n\tSysTick->VAL=0;\n\tSysTick->CTRL=0x5;\n\t\tfor (int i=0;i<ms;i++)\n\t\t{\n\t\t\twhile(!(SysTick->CTRL &0x10000)){}\n\t\t}\n\tSysTick->CTRL=0;\n}<\/pre><\/div>\n\n\n\n6. Download source Code<\/h2>\n\n\n\n