{"id":2729,"date":"2024-08-11T03:49:12","date_gmt":"2024-08-11T03:49:12","guid":{"rendered":"https:\/\/blog.embeddedexpert.io\/?p=2729"},"modified":"2024-08-11T03:49:15","modified_gmt":"2024-08-11T03:49:15","slug":"cache-in-arm-cortex-m7-mpu-attributes-and-memory-types","status":"publish","type":"post","link":"https:\/\/blog.embeddedexpert.io\/?p=2729","title":{"rendered":"Cache in ARM Cortex M7: MPU Attributes and Memory types"},"content":{"rendered":"\n<figure class=\"wp-block-image size-large\"><img loading=\"lazy\" decoding=\"async\" width=\"1024\" height=\"586\" src=\"https:\/\/blog.embeddedexpert.io\/wp-content\/uploads\/2024\/08\/fig2.png-3-1024x586.webp\" alt=\"\" class=\"wp-image-2730\" srcset=\"https:\/\/blog.embeddedexpert.io\/wp-content\/uploads\/2024\/08\/fig2.png-3-1024x586.webp 1024w, https:\/\/blog.embeddedexpert.io\/wp-content\/uploads\/2024\/08\/fig2.png-3-300x172.webp 300w, https:\/\/blog.embeddedexpert.io\/wp-content\/uploads\/2024\/08\/fig2.png-3-768x440.webp 768w, https:\/\/blog.embeddedexpert.io\/wp-content\/uploads\/2024\/08\/fig2.png-3-1150x658.webp 1150w, https:\/\/blog.embeddedexpert.io\/wp-content\/uploads\/2024\/08\/fig2.png-3-750x429.webp 750w, https:\/\/blog.embeddedexpert.io\/wp-content\/uploads\/2024\/08\/fig2.png-3-400x229.webp 400w, https:\/\/blog.embeddedexpert.io\/wp-content\/uploads\/2024\/08\/fig2.png-3-250x143.webp 250w, https:\/\/blog.embeddedexpert.io\/wp-content\/uploads\/2024\/08\/fig2.png-3.webp 1310w\" sizes=\"(max-width: 1024px) 100vw, 1024px\" \/><\/figure>\n\n\n\n<p>In this guide, we shall take a look at the memory types in ARM Cortex M7 and the attribute the of the MPU.<\/p>\n\n\n\n<p><\/p>\n\n\n\n<p>This guide shall cover the following:<\/p>\n\n\n\n<ul class=\"wp-block-list\"><li>Memory types.<\/li><li>MPU attributes.<\/li><li>Important tips.<\/li><li>MPU configurations.<\/li><\/ul>\n\n\n\n<h2 class=\"wp-block-heading\">4. Memory Types:<\/h2>\n\n\n\n<p>The memory in ARM Cortex M7 is classified as following:<\/p>\n\n\n\n<ul class=\"wp-block-list\"><li>Normal Memory.<\/li><li>Device Memory.<\/li><li>Strongly ordered Memory.<\/li><\/ul>\n\n\n\n<p><\/p>\n\n\n\n<p><\/p>\n\n\n\n<figure class=\"wp-block-image size-large\"><img loading=\"lazy\" decoding=\"async\" width=\"1024\" height=\"297\" src=\"https:\/\/blog.embeddedexpert.io\/wp-content\/uploads\/2024\/08\/image-4-1024x297.png\" alt=\"\" class=\"wp-image-2731\" srcset=\"https:\/\/blog.embeddedexpert.io\/wp-content\/uploads\/2024\/08\/image-4-1024x297.png 1024w, https:\/\/blog.embeddedexpert.io\/wp-content\/uploads\/2024\/08\/image-4-300x87.png 300w, https:\/\/blog.embeddedexpert.io\/wp-content\/uploads\/2024\/08\/image-4-768x223.png 768w, https:\/\/blog.embeddedexpert.io\/wp-content\/uploads\/2024\/08\/image-4-1150x333.png 1150w, https:\/\/blog.embeddedexpert.io\/wp-content\/uploads\/2024\/08\/image-4-750x217.png 750w, https:\/\/blog.embeddedexpert.io\/wp-content\/uploads\/2024\/08\/image-4-400x116.png 400w, https:\/\/blog.embeddedexpert.io\/wp-content\/uploads\/2024\/08\/image-4-250x72.png 250w, https:\/\/blog.embeddedexpert.io\/wp-content\/uploads\/2024\/08\/image-4.png 1346w\" sizes=\"(max-width: 1024px) 100vw, 1024px\" \/><\/figure>\n\n\n\n<p><\/p>\n\n\n\n<ul class=\"wp-block-list\"><li>Normal memory is good for code execution.<\/li><li>It allows the speculative access.<\/li><li>No speculative access in strongly ordered and device memories.<\/li><li>CPU waits for the end of instruction before performing another one.<\/li><li>Each write needs to be visible for device,\u00a0eg- external NAND.<\/li><li>Device memory is used for microcontroller Registers.<\/li><\/ul>\n\n\n\n<p> <\/p>\n\n\n\n<p>Here is the default memory access behavior for ARM Cortex M7:<\/p>\n\n\n\n<figure class=\"wp-block-image size-large\"><img loading=\"lazy\" decoding=\"async\" width=\"1024\" height=\"863\" src=\"https:\/\/blog.embeddedexpert.io\/wp-content\/uploads\/2024\/08\/image-5-1024x863.png\" alt=\"\" class=\"wp-image-2733\" srcset=\"https:\/\/blog.embeddedexpert.io\/wp-content\/uploads\/2024\/08\/image-5-1024x863.png 1024w, https:\/\/blog.embeddedexpert.io\/wp-content\/uploads\/2024\/08\/image-5-300x253.png 300w, https:\/\/blog.embeddedexpert.io\/wp-content\/uploads\/2024\/08\/image-5-768x647.png 768w, https:\/\/blog.embeddedexpert.io\/wp-content\/uploads\/2024\/08\/image-5-1150x969.png 1150w, https:\/\/blog.embeddedexpert.io\/wp-content\/uploads\/2024\/08\/image-5-750x632.png 750w, https:\/\/blog.embeddedexpert.io\/wp-content\/uploads\/2024\/08\/image-5-400x337.png 400w, https:\/\/blog.embeddedexpert.io\/wp-content\/uploads\/2024\/08\/image-5-250x211.png 250w, https:\/\/blog.embeddedexpert.io\/wp-content\/uploads\/2024\/08\/image-5.png 1234w\" sizes=\"(max-width: 1024px) 100vw, 1024px\" \/><\/figure>\n\n\n\n<p><\/p>\n\n\n\n<h2 class=\"wp-block-heading\">5. MPU Attributes:<\/h2>\n\n\n\n<p>The MPU attributes in ARM Cortex M7 have the following:<\/p>\n\n\n\n<ul class=\"wp-block-list\"><li>Shareability.<\/li><li>Cacheablility.<\/li><li>Bufferability.<\/li><li>Executable Never.<\/li><\/ul>\n\n\n\n<h2 class=\"wp-block-heading\">5.1 Sharable Region:<\/h2>\n\n\n\n<ul class=\"wp-block-list\"><li>Means multiple master can access the memory region (e.g. DMA and CPU).<\/li><li>Strongly Ordered Memory is always sharable.<\/li><li>If there is an area is cacheable and shareable, Data cache can&#8217;t be used and instruction caching can be used.<\/li><\/ul>\n\n\n\n<p>A great example for sharable region in STM32H757 is the ethernet:<\/p>\n\n\n\n<figure class=\"wp-block-image size-full\"><img loading=\"lazy\" decoding=\"async\" width=\"880\" height=\"254\" src=\"https:\/\/blog.embeddedexpert.io\/wp-content\/uploads\/2024\/08\/image-6.png\" alt=\"\" class=\"wp-image-2734\" srcset=\"https:\/\/blog.embeddedexpert.io\/wp-content\/uploads\/2024\/08\/image-6.png 880w, https:\/\/blog.embeddedexpert.io\/wp-content\/uploads\/2024\/08\/image-6-300x87.png 300w, https:\/\/blog.embeddedexpert.io\/wp-content\/uploads\/2024\/08\/image-6-768x222.png 768w, https:\/\/blog.embeddedexpert.io\/wp-content\/uploads\/2024\/08\/image-6-750x216.png 750w, https:\/\/blog.embeddedexpert.io\/wp-content\/uploads\/2024\/08\/image-6-400x115.png 400w, https:\/\/blog.embeddedexpert.io\/wp-content\/uploads\/2024\/08\/image-6-250x72.png 250w\" sizes=\"(max-width: 880px) 100vw, 880px\" \/><\/figure>\n\n\n\n<p>Here, we are allocating 256 Byte as sharable, bufferable but not cacheable at all.<\/p>\n\n\n\n<p><\/p>\n\n\n\n<h2 class=\"wp-block-heading\">5.2 Cacheable Region:<\/h2>\n\n\n\n<p>As mentioned in the previous parts, it is the region where the caches (data and instruction) can be used.<\/p>\n\n\n\n<p>In case multiple master is used, the cache needed to be disabled to ensure synchronous operation of multiple masters.<\/p>\n\n\n\n<p>Later, we shall see how to configure the MPU to disable the cache for certain region.<\/p>\n\n\n\n<p><\/p>\n\n\n\n<h2 class=\"wp-block-heading\">5.3: Execute Never(XN):<\/h2>\n\n\n\n<p>This type is used to set the region where no instruction shall be executed from, trying to access this region will cause hard fault.<\/p>\n\n\n\n<p>For example for NX is when to use external memory as internal flash (Memory Mapped Mode):<\/p>\n\n\n\n<figure class=\"wp-block-image size-full\"><img loading=\"lazy\" decoding=\"async\" width=\"962\" height=\"284\" src=\"https:\/\/blog.embeddedexpert.io\/wp-content\/uploads\/2024\/08\/image-7.png\" alt=\"\" class=\"wp-image-2735\" srcset=\"https:\/\/blog.embeddedexpert.io\/wp-content\/uploads\/2024\/08\/image-7.png 962w, https:\/\/blog.embeddedexpert.io\/wp-content\/uploads\/2024\/08\/image-7-300x89.png 300w, https:\/\/blog.embeddedexpert.io\/wp-content\/uploads\/2024\/08\/image-7-768x227.png 768w, https:\/\/blog.embeddedexpert.io\/wp-content\/uploads\/2024\/08\/image-7-750x221.png 750w, https:\/\/blog.embeddedexpert.io\/wp-content\/uploads\/2024\/08\/image-7-400x118.png 400w, https:\/\/blog.embeddedexpert.io\/wp-content\/uploads\/2024\/08\/image-7-250x74.png 250w\" sizes=\"(max-width: 962px) 100vw, 962px\" \/><\/figure>\n\n\n\n<p><\/p>\n\n\n\n<p><\/p>\n\n\n\n<p>Here, we are setting the address to be QSPI address (0x9000 0000) and the size is 16MB which is the size of the external flash , the region is cacheable, bufferable, not shareable and instruction access is disabled (XN).<\/p>\n\n\n\n<p>This way, if the application needed to execute an instruction from this region, it will generate hardfault.<\/p>\n\n\n\n<p><\/p>\n\n\n\n<h2 class=\"wp-block-heading\">6. Important Tips:<\/h2>\n\n\n\n<figure class=\"wp-block-image size-large\"><img loading=\"lazy\" decoding=\"async\" width=\"1024\" height=\"350\" src=\"https:\/\/blog.embeddedexpert.io\/wp-content\/uploads\/2024\/08\/image-8-1024x350.png\" alt=\"\" class=\"wp-image-2736\" srcset=\"https:\/\/blog.embeddedexpert.io\/wp-content\/uploads\/2024\/08\/image-8-1024x350.png 1024w, https:\/\/blog.embeddedexpert.io\/wp-content\/uploads\/2024\/08\/image-8-300x103.png 300w, https:\/\/blog.embeddedexpert.io\/wp-content\/uploads\/2024\/08\/image-8-768x262.png 768w, https:\/\/blog.embeddedexpert.io\/wp-content\/uploads\/2024\/08\/image-8-750x256.png 750w, https:\/\/blog.embeddedexpert.io\/wp-content\/uploads\/2024\/08\/image-8-400x137.png 400w, https:\/\/blog.embeddedexpert.io\/wp-content\/uploads\/2024\/08\/image-8-250x85.png 250w, https:\/\/blog.embeddedexpert.io\/wp-content\/uploads\/2024\/08\/image-8.png 1112w\" sizes=\"(max-width: 1024px) 100vw, 1024px\" \/><\/figure>\n\n\n\n<p><\/p>\n\n\n\n<p><\/p>\n\n\n\n<h2 class=\"wp-block-heading\">7. MPU Configuration:<\/h2>\n\n\n\n<figure class=\"wp-block-image size-large\"><img loading=\"lazy\" decoding=\"async\" width=\"1024\" height=\"536\" src=\"https:\/\/blog.embeddedexpert.io\/wp-content\/uploads\/2024\/08\/image-9-1024x536.png\" alt=\"\" class=\"wp-image-2737\" srcset=\"https:\/\/blog.embeddedexpert.io\/wp-content\/uploads\/2024\/08\/image-9-1024x536.png 1024w, https:\/\/blog.embeddedexpert.io\/wp-content\/uploads\/2024\/08\/image-9-300x157.png 300w, https:\/\/blog.embeddedexpert.io\/wp-content\/uploads\/2024\/08\/image-9-768x402.png 768w, https:\/\/blog.embeddedexpert.io\/wp-content\/uploads\/2024\/08\/image-9-750x392.png 750w, https:\/\/blog.embeddedexpert.io\/wp-content\/uploads\/2024\/08\/image-9-400x209.png 400w, https:\/\/blog.embeddedexpert.io\/wp-content\/uploads\/2024\/08\/image-9-250x131.png 250w, https:\/\/blog.embeddedexpert.io\/wp-content\/uploads\/2024\/08\/image-9.png 1128w\" sizes=\"(max-width: 1024px) 100vw, 1024px\" \/><\/figure>\n\n\n\n<p><\/p>\n","protected":false},"excerpt":{"rendered":"<p>In this guide, we shall take a look at the memory types in ARM Cortex M7 and the attribute the of the MPU. This guide shall cover the following: Memory types. MPU attributes. Important tips. MPU configurations. 4. Memory Types: The memory in ARM Cortex M7 is classified as following: Normal Memory. Device Memory. Strongly [&hellip;]<\/p>\n","protected":false},"author":2,"featured_media":0,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"footnotes":""},"categories":[2,12],"tags":[],"class_list":["post-2729","post","type-post","status-publish","format-standard","hentry","category-embedded-systems","category-stm32"],"_links":{"self":[{"href":"https:\/\/blog.embeddedexpert.io\/index.php?rest_route=\/wp\/v2\/posts\/2729"}],"collection":[{"href":"https:\/\/blog.embeddedexpert.io\/index.php?rest_route=\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/blog.embeddedexpert.io\/index.php?rest_route=\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/blog.embeddedexpert.io\/index.php?rest_route=\/wp\/v2\/users\/2"}],"replies":[{"embeddable":true,"href":"https:\/\/blog.embeddedexpert.io\/index.php?rest_route=%2Fwp%2Fv2%2Fcomments&post=2729"}],"version-history":[{"count":2,"href":"https:\/\/blog.embeddedexpert.io\/index.php?rest_route=\/wp\/v2\/posts\/2729\/revisions"}],"predecessor-version":[{"id":2738,"href":"https:\/\/blog.embeddedexpert.io\/index.php?rest_route=\/wp\/v2\/posts\/2729\/revisions\/2738"}],"wp:attachment":[{"href":"https:\/\/blog.embeddedexpert.io\/index.php?rest_route=%2Fwp%2Fv2%2Fmedia&parent=2729"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/blog.embeddedexpert.io\/index.php?rest_route=%2Fwp%2Fv2%2Fcategories&post=2729"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/blog.embeddedexpert.io\/index.php?rest_route=%2Fwp%2Fv2%2Ftags&post=2729"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}