![\"\"](\"https:\/\/blog.embeddedexpert.io\/wp-content\/uploads\/2023\/10\/AdobeStock_495094833-1024x654.jpeg\")
<\/figure>\n\n\n\nIn this guide, we shall develop driver to measure the frequency and duty cycle of a signal.<\/p>\n\n\n\n
<\/p>\n\n\n\n
In this guide, we shall cover the following:<\/p>\n\n\n\n
- What is PWM input mode.<\/li>
- Required steps.<\/li>
- Driver.<\/li>
- STM32 Connection<\/li>
- Code.<\/li>
- Results.<\/li><\/ul>\n\n\n\n
<\/p>\n\n\n\n
1. What is PWM Input Mode:<\/h2>\n\n\n\n
<\/p>\n\n\n\n
PWM input mode is similar to input capture mode (explained here<\/a>) with the following differences:<\/p>\n\n\n\n
Two ICx signals are mapped on the same TIx input.<\/p>\n\n\n\n
These 2 ICx signals are active on edges with opposite polarity.<\/p>\n\n\n\n
One of the two TIxFP signals is selected as trigger input and the slave mode controller is configured in reset mode.<\/p>\n\n\n\n
For example, one can measure the period (in TIMx_CCR1 register) and the duty cycle (in TIMx_CCR2 register) of the PWM applied on TI1.<\/p>\n\n\n\n
<\/p>\n\n\n\n
The timing diagram as following:<\/p>\n\n\n\n
![\"\"](\"https:\/\/blog.embeddedexpert.io\/wp-content\/uploads\/2023\/10\/Screenshot-2023-10-05-at-7.28.56-AM-1024x530.png\")
<\/figure>\n\n\n\n<\/p>\n\n\n\n
When an rising edge is detected, the IC1 is capture and IC2 is reset. When fall edge is detected, IC2 capture the duty cycle (pulse width). The cycles continues.<\/p>\n\n\n\n
<\/p>\n\n\n\n
To measure the frequency, the following equation can be used:<\/p>\n\n\n\n
![\"\"](\"https:\/\/blog.embeddedexpert.io\/wp-content\/uploads\/2023\/10\/Screenshot-2023-10-05-at-7.33.16-AM-1024x189.png\")
<\/figure>\n\n\n\n<\/p>\n\n\n\n
For the duty cycle:<\/p>\n\n\n\n
<\/p>\n\n\n\n
![\"\"](\"https:\/\/blog.embeddedexpert.io\/wp-content\/uploads\/2023\/10\/Screenshot-2023-10-05-at-7.35.22-AM-1024x155.png\")
<\/figure>\n\n\n\n<\/p>\n\n\n\n
<\/p>\n\n\n\n
That all for the theory of PWM input mode.<\/p>\n\n\n\n
<\/p>\n\n\n\n
<\/p>\n\n\n\n
2. Required steps:<\/h2>\n\n\n\n
<\/p>\n\n\n\n
The required steps as following:<\/p>\n\n\n\n
<\/p>\n\n\n\n
![\"\"](\"https:\/\/blog.embeddedexpert.io\/wp-content\/uploads\/2023\/10\/Screenshot-2023-10-05-at-7.37.30-AM-1024x439.png\")
<\/figure>\n\n\n\n<\/p>\n\n\n\n
3. Developing the Driver:<\/h2>\n\n\n\n
This guide shall use timer2 to measure the frequency and duty cycle of a signal applied to PA0 and PWM signal generated from PA8 connected to TIM1. For timer 1 PWM generation, please refer to this<\/a> guide. Also, the core is set to 100MHz from here<\/a>.<\/p>\n\n\n\n
<\/p>\n\n\n\n
Since the signal is connected to PA0 and this pin is connected to TIM2, we shall enable clock access to GPIOA as following:<\/p>\n\n\n\n
<\/p>\n\n\n\n
\t\/*Enable clock access to GPIOA*\/\n\tRCC->AHB1ENR|=RCC_AHB1ENR_GPIOAEN;<\/pre><\/div>\n\n\n\n
Set PA0 to alternate function and select which alternate function as following:<\/p>\n\n\n\n
\t\/*Set PA0 and PA1 to alternate function*\/\n\tGPIOA->MODER|=(GPIO_MODER_MODE0_1);\n\tGPIOA->MODER&=~(GPIO_MODER_MODE0_0);\n\n\t\/*Select AF01 for TIM2*\/\n\t#define AF01 0x01\n\tGPIOA->AFR[0]|=(AF01<<GPIO_AFRL_AFSEL0_Pos)|(AF01<<GPIO_AFRL_AFSEL1_Pos);<\/pre><\/div>\n\n\n\n
Thats all for the GPIO configuration, next timer configuration. <\/p>\n\n\n\n
We start off by enabling clock access to TIM2 (please refer to this guide<\/a> for more details how to enable clock access):<\/p>\n\n\n\n
\t\/*enable clock access to tim2*\/\n\tRCC->APB1ENR|=RCC_APB1ENR_TIM2EN;<\/pre><\/div>\n\n\n\n
Set prescaller to 0 to get full speed:<\/p>\n\n\n\n
\t\/*set the prescaler to 0 to get 100MHZ*\/\n\tTIM2->PSC=0;<\/pre><\/div>\n\n\n\n
Set the Auto reload value to maximum (32-bit value):<\/p>\n\n\n\n
\t\/*set the maximum to 199999 to get 5 Hz update rate*\/\n\tTIM2->ARR=0xFFFFFFFF;<\/pre><\/div>\n\n\n\n
Reset the counter:<\/p>\n\n\n\n
\t\/*Reset current counter*\/\n\tTIM2->CNT=0;<\/pre><\/div>\n\n\n\n
Set CH1 to input mapped to TI1 as following:<\/p>\n\n\n\n
\t\/*Set TIM2_Ch1 to be input mapped to TI1*\/\n\tTIM2->CCMR1|=TIM_CCMR1_CC1S_0;<\/pre><\/div>\n\n\n\n
Set the trigger to be rising edge:<\/p>\n\n\n\n
\t\/*Select TIM2 CH1 to be Rising edge*\/\n\tTIM2->CCER&=~(TIM_CCER_CC1P|TIM_CCER_CC1NP);<\/pre><\/div>\n\n\n\n
Set CH2 as input mapped to TI1 as following:<\/p>\n\n\n\n
\t\/*Set TIM2_CH2 to be input mapped to TI1*\/\n\tTIM2->CCMR1|=TIM_CCMR1_CC2S_1;<\/pre><\/div>\n\n\n\n
Set the detection edge to be falling edge:<\/p>\n\n\n\n
\t\/*Select TIM2 CH1 to be Falling edge*\/\n\tTIM2->CCER|=TIM_CCER_CC2P;\n\tTIM2->CCER&=~TIM_CCER_CC2NP;<\/pre><\/div>\n\n\n\n
Set trigger mode to be filtered Timer Input 1 as following:<\/p>\n\n\n\n
\t\/*Set trigger mode to be Filtered Timer Input 1*\/\n\tTIM2->SMCR|=TIM_SMCR_TS_2|TIM_SMCR_TS_0;<\/pre><\/div>\n\n\n\n
Set the slave mode to be reset mode:<\/p>\n\n\n\n
\t\/*Set the slave mode to be reset mode*\/\n\tTIM2->SMCR|=TIM_SMCR_SMS_2;<\/pre><\/div>\n\n\n\n
Enable both channel:<\/p>\n\n\n\n
\t\/*Enable both channel*\/\n\tTIM2->CCER|=TIM_CCER_CC1E|TIM_CCER_CC2E;<\/pre><\/div>\n\n\n\n
Enable DMA for both channel as following:<\/p>\n\n\n\n
\t\/*Enable DMA for both channel*\/\n\n\tTIM2->DIER|=TIM_DIER_CC1DE|TIM_DIER_CC2DE;<\/pre><\/div>\n\n\n\n
For DMA configuration (covered here<\/a>):<\/p>\n\n\n\n
\/*DMA configuration*\/\n\n\t\/*Enable clock access to DMA1*\/\n\n\tRCC->AHB1ENR|=RCC_AHB1ENR_DMA1EN;\n\n\t\/*Disable the stream and wait until it is disabled*\/\n\tDMA1_Stream6->CR &=~DMA_SxCR_EN;\n\n\twhile((DMA1_Stream6->CR & DMA_SxCR_EN) == DMA_SxCR_EN );\n\n\t\/*Configure the DMA with the following parameters\n\t *\n\t * Channel is channel 3\n\t * Memory and peripheral size is word (32-bit)\n\t * Circular mode\n\t *\n\t * *\/\n\n\n\t#define CH3 0x03\n\n\tDMA1_Stream6->CR |= (CH3<<DMA_SxCR_CHSEL_Pos)|DMA_SxCR_PSIZE_1|DMA_SxCR_MSIZE_1|DMA_SxCR_CIRC;\n\n\t\/*Set number of transfers to be 1\n\t * Peripheral address to TIM2->CCR2\n\t * Memory address to be the period variable\n\t * *\/\n\tDMA1_Stream6->NDTR=1;\n\tDMA1_Stream6->PAR= (uint32_t)&TIM2->CCR2;\n\tDMA1_Stream6->M0AR=(uint32_t)&duty_cycle;\n\n\t\/*Enable DMA*\/\n\tDMA1_Stream6->CR |=DMA_SxCR_EN;\n\n\n\n\t\/*Disable the stream and wait until it is disabled*\/\n\tDMA1_Stream5->CR &=~DMA_SxCR_EN;\n\n\twhile((DMA1_Stream5->CR & DMA_SxCR_EN) == DMA_SxCR_EN );\n\n\t\/*Configure the DMA with the following parameters\n\t *\n\t * Channel is channel 3\n\t * Memory and peripheral size is word (32-bit)\n\t * Circular mode\n\t *\n\t * *\/\n\n\tDMA1_Stream5->CR |= (CH3<<DMA_SxCR_CHSEL_Pos)|DMA_SxCR_PSIZE_1|DMA_SxCR_MSIZE_1|DMA_SxCR_CIRC;\n\n\t\/*Set number of transfers to be 1\n\t * Peripheral address to TIM2->CCR1\n\t * Memory address to be the period variable\n\t * *\/\n\tDMA1_Stream5->NDTR=1;\n\tDMA1_Stream5->PAR= (uint32_t)&TIM2->CCR1;\n\tDMA1_Stream5->M0AR=(uint32_t).\n\n\t\/*Enable DMA*\/\n\tDMA1_Stream5->CR |=DMA_SxCR_EN;<\/pre><\/div>\n\n\n\n
Finally enable the timer:<\/p>\n\n\n\n
\t\/*Enable timer*\/\n\tTIM2->CR1=TIM_CR1_CEN;<\/pre><\/div>\n\n\n\n
In while 1 loop:<\/p>\n\n\n\n
We simply calculate the duty cycle and frequency as per equation mentioned earlier: <\/p>\n\n\n\n
Don’t forget to add 1 to both values to get the correct values<\/p>\n\n\n\n
\t\tfrequency=(float)(100000000\/(period+1));\n\n\t\tdutyCycle=(float)(((duty_cycle+1)*100)\/(period));\n\n\t\tprintf("Period is %ld\\r\\n",frequency);\n\n\t\tprintf("Duty cycle is %ld\\r\\n",dutyCycle);\n\t\tdelay(200);<\/pre><\/div>\n\n\n\nHence, the entire code as following:<\/p>\n\n\n\n
#include "delay.h"\n#include "uart.h"\n#include "stdio.h"\n#include "pwm_generator.h"\n\nextern void SysClockConfig(void);\n\n\/*Variable to hold the measured pulse length*\/\nuint32_t period;\n\n\/*Variable to hold the measured duty cycle*\/\nuint32_t duty_cycle;\n\n\n\/*variable to hold the measured distance*\/\nuint32_t frequency, dutyCycle;\n\nint main(void)\n{\n\n\n\n\t\/*Enable float point hardware*\/\n\tSCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2));\n\t\/*Set the clock to 100MHz*\/\n\tSysClockConfig();\n\n\t\/*Initialize UART2*\/\n\tuart2_init();\n\n\t\/*Initialize TIM1 as PWM\n\t * Prescaller 0\n\t * ARR value of 600\n\t * CCR1 value of 300 (50%)\n\t * *\/\n\t\n\tTIM1_PWM_Init(0,600,300);\n\n\t\/*Enable clock access to GPIOA*\/\n\tRCC->AHB1ENR|=RCC_AHB1ENR_GPIOAEN;\n\n\t\/*Set PA0 and PA1 to alternate function*\/\n\tGPIOA->MODER|=(GPIO_MODER_MODE0_1);\n\tGPIOA->MODER&=~(GPIO_MODER_MODE0_0);\n\n\t\/*Select AF01 for TIM2*\/\n\t#define AF01 0x01\n\tGPIOA->AFR[0]|=(AF01<<GPIO_AFRL_AFSEL0_Pos)|(AF01<<GPIO_AFRL_AFSEL1_Pos);\n\n\t\/*enable clock access to tim2*\/\n\tRCC->APB1ENR|=RCC_APB1ENR_TIM2EN;\n\n\t\/*set the prescaler to 0 to get 100MHZ*\/\n\tTIM2->PSC=0;\n\n\t\/*set the maximum to 199999 to get 5 Hz update rate*\/\n\tTIM2->ARR=0xFFFFFFFF;\n\n\t\/*Reset current counter*\/\n\tTIM2->CNT=0;\n\n\t\/*Set TIM2_Ch1 to be input mapped to TI1*\/\n\tTIM2->CCMR1|=TIM_CCMR1_CC1S_0;\n\n\t\/*Select TIM2 CH1 to be Rising edge*\/\n\tTIM2->CCER&=~(TIM_CCER_CC1P|TIM_CCER_CC1NP);\n\n\t\/*Set TIM2_CH2 to be input mapped to TI1*\/\n\tTIM2->CCMR1|=TIM_CCMR1_CC2S_1;\n\n\t\/*Select TIM2 CH1 to be Falling edge*\/\n\tTIM2->CCER|=TIM_CCER_CC2P;\n\tTIM2->CCER&=~TIM_CCER_CC2NP;\n\n\t\/*Set trigger mode to be Filtered Timer Input 1*\/\n\tTIM2->SMCR|=TIM_SMCR_TS_2|TIM_SMCR_TS_0;\n\n\t\/*Set the slave mode to be reset mode*\/\n\tTIM2->SMCR|=TIM_SMCR_SMS_2;\n\n\t\/*Enable both channel*\/\n\tTIM2->CCER|=TIM_CCER_CC1E|TIM_CCER_CC2E;\n\n\t\/*Enable DMA for both channel*\/\n\n\tTIM2->DIER|=TIM_DIER_CC1DE|TIM_DIER_CC2DE;\n\n\n\t\/*DMA configuration*\/\n\n\t\/*Enable clock access to DMA1*\/\n\n\tRCC->AHB1ENR|=RCC_AHB1ENR_DMA1EN;\n\n\t\/*Disable the stream and wait until it is disabled*\/\n\tDMA1_Stream6->CR &=~DMA_SxCR_EN;\n\n\twhile((DMA1_Stream6->CR & DMA_SxCR_EN) == DMA_SxCR_EN );\n\n\t\/*Configure the DMA with the following parameters\n\t *\n\t * Channel is channel 3\n\t * Memory and peripheral size is word (32-bit)\n\t * Circular mode\n\t *\n\t * *\/\n\n\n\t#define CH3 0x03\n\n\tDMA1_Stream6->CR |= (CH3<<DMA_SxCR_CHSEL_Pos)|DMA_SxCR_PSIZE_1|DMA_SxCR_MSIZE_1|DMA_SxCR_CIRC;\n\n\t\/*Set number of transfers to be 1\n\t * Peripheral address to TIM2->CCR2\n\t * Memory address to be the period variable\n\t * *\/\n\tDMA1_Stream6->NDTR=1;\n\tDMA1_Stream6->PAR= (uint32_t)&TIM2->CCR2;\n\tDMA1_Stream6->M0AR=(uint32_t)&duty_cycle;\n\n\t\/*Enable DMA*\/\n\tDMA1_Stream6->CR |=DMA_SxCR_EN;\n\n\n\n\t\/*Disable the stream and wait until it is disabled*\/\n\tDMA1_Stream5->CR &=~DMA_SxCR_EN;\n\n\twhile((DMA1_Stream5->CR & DMA_SxCR_EN) == DMA_SxCR_EN );\n\n\t\/*Configure the DMA with the following parameters\n\t *\n\t * Channel is channel 3\n\t * Memory and peripheral size is word (32-bit)\n\t * Circular mode\n\t *\n\t * *\/\n\n\tDMA1_Stream5->CR |= (CH3<<DMA_SxCR_CHSEL_Pos)|DMA_SxCR_PSIZE_1|DMA_SxCR_MSIZE_1|DMA_SxCR_CIRC;\n\n\t\/*Set number of transfers to be 1\n\t * Peripheral address to TIM2->CCR1\n\t * Memory address to be the period variable\n\t * *\/\n\tDMA1_Stream5->NDTR=1;\n\tDMA1_Stream5->PAR= (uint32_t)&TIM2->CCR1;\n\tDMA1_Stream5->M0AR=(uint32_t).\n\n\t\/*Enable DMA*\/\n\tDMA1_Stream5->CR |=DMA_SxCR_EN;\n\n\t\/*Enable timer*\/\n\tTIM2->CR1=TIM_CR1_CEN;\n\n\n\n\twhile(1)\n\t{\n\n\t\tfrequency=(float)(100000000\/(period+1));\n\n\t\tdutyCycle=(float)(((duty_cycle+1)*100)\/(period));\n\n\t\tprintf("Period is %ld\\r\\n",frequency);\n\n\t\tprintf("Duty cycle is %ld\\r\\n",dutyCycle);\n\t\tdelay(200);\n\n\n\t}\n\n}\n\n\n<\/pre><\/div>\n\n\n\n<\/p>\n\n\n\n
<\/p>\n\n\n\n
4. STM32 Connection:<\/h2>\n\n\n\n
The connection as following:<\/p>\n\n\n\n
![\"\"](\"https:\/\/blog.embeddedexpert.io\/wp-content\/uploads\/2023\/10\/Screenshot-2023-10-05-at-7.41.09-AM-832x1024.png\")
<\/figure>\n\n\n\n<\/h2>\n\n\n\n
Simple, just connect a wire from PA8 to PA0.<\/p>\n\n\n\n
<\/p>\n\n\n\n
5. Code:<\/h2>\n\n\n\n
You may download the code from here:<\/p>\n\n\n\n
PWM_Input<\/a>Download<\/a><\/div>\n\n\n\n<\/p>\n\n\n\n
<\/p>\n\n\n\n
6. Results:<\/h2>\n\n\n\n
Since timer1 is configured with prescaler of 0 and ARR value of 600, this would give PWM signal with frequency of 166666Hz which is proven by measured value using PWM input:<\/p>\n\n\n\n
Open serial terminal and set the baud to 115200 and you should get the following:<\/p>\n\n\n\n
<\/p>\n\n\n\n
![\"\"](\"https:\/\/blog.embeddedexpert.io\/wp-content\/uploads\/2023\/10\/Screenshot-2023-10-05-at-8.15.35-AM-172x1024.png\")
<\/figure>\n\n\n\nHappy coding \ud83d\ude42<\/p>\n","protected":false},"excerpt":{"rendered":"
In this guide, we shall develop driver to measure the frequency and duty cycle of a signal. In this guide, we shall cover the following: What is PWM input mode. Required steps. Driver. STM32 Connection Code. Results. 1. What is PWM Input Mode: PWM input mode is similar to input capture mode (explained here) with […]<\/p>\n","protected":false},"author":2,"featured_media":0,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"footnotes":""},"categories":[2,11,12],"tags":[],"class_list":["post-2019","post","type-post","status-publish","format-standard","hentry","category-embedded-systems","category-peripheral-drivers","category-stm32"],"_links":{"self":[{"href":"https:\/\/blog.embeddedexpert.io\/index.php?rest_route=\/wp\/v2\/posts\/2019"}],"collection":[{"href":"https:\/\/blog.embeddedexpert.io\/index.php?rest_route=\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/blog.embeddedexpert.io\/index.php?rest_route=\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/blog.embeddedexpert.io\/index.php?rest_route=\/wp\/v2\/users\/2"}],"replies":[{"embeddable":true,"href":"https:\/\/blog.embeddedexpert.io\/index.php?rest_route=%2Fwp%2Fv2%2Fcomments&post=2019"}],"version-history":[{"count":2,"href":"https:\/\/blog.embeddedexpert.io\/index.php?rest_route=\/wp\/v2\/posts\/2019\/revisions"}],"predecessor-version":[{"id":2029,"href":"https:\/\/blog.embeddedexpert.io\/index.php?rest_route=\/wp\/v2\/posts\/2019\/revisions\/2029"}],"wp:attachment":[{"href":"https:\/\/blog.embeddedexpert.io\/index.php?rest_route=%2Fwp%2Fv2%2Fmedia&parent=2019"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/blog.embeddedexpert.io\/index.php?rest_route=%2Fwp%2Fv2%2Fcategories&post=2019"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/blog.embeddedexpert.io\/index.php?rest_route=%2Fwp%2Fv2%2Ftags&post=2019"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}